A wide variety of interface protocols are used for data exchange among computers, peripheral devices such as hard disk drives and scanners, and cellular phone, digital camera, and video systems. A one-chip microprocessor, which is integrated with a CPU core and peripheral IPs conforming to various interface protocols, is developed to support a wide variety of interfaces. The term “peripheral IPs” used in the present application refers to circuit modules that provide an interface for connecting the CPU core to external devices.
Within this type of microprocessor, all of its peripheral IPs are not used at all times. Since some peripheral IPs are not used, it is necessary to exercise control so as to enable/disable the peripheral IPs.
One control method is to provide each peripheral IP with a control register so that the CPU core enters a command for each control register via a peripheral bus to specify whether the associated peripheral IP should be enabled or disabled (first conventional technology).
The method stated in JP-A No. 289051/1999 is to use a programmable circuit, which is typically represented by an FPGA. A programmable circuit is integrated with an MPU and various interface circuits. This programmable circuit is used after LSI manufacture to determine the wiring connections between the MPU and various interface circuits. As a result, various interface sets can be supported by a single LSI (second conventional technology).
As the number of interfaces to be supported by the CPU core, the number of peripheral IPs increases, causing the following problems:
When the first conventional technology is used, the increase in the number of peripheral IPs may increase the number of output pins, thereby raising the package price. Further, even when some peripheral IP circuits are disabled by a command, they still run in a sleep mode, allowing unnecessary power consumption to continue. The term “sleep mode” refers to a mode of operation in which the command transmission from the CPU or a device outside the LSI is monitored. If there are many unnecessary peripheral IPs, the software designer may also be perplexed.
When the second conventional technology is used, the MPU and interface circuits are directly connected by the programmable circuit. Therefore, the resulting configuration differs from the microprocessor's common configuration, which is established via a bus. That is why the configuration based on the second conventional technology is inapplicable to general-purpose processors. Further, the second conventional technology has not disclosed a configuration that would reduce the amount of unnecessary power consumption.
In a volume production of an LSI, it is possible to develop an LSI that carries only necessary peripheral IPs. In limited production of diversified products, however, the development cost of such an LSI would prove to be excessive. If a single kind of LSI could be commonly used for limited production of diversified products, it would be possible to reduce the development cost and shorten the development period.